Efficient Macromodeling of Defect Propagation/Growth Mechanisms in VLSI Fabrication

Particulate contamination deposited on silicon wafers is typically the dominant reason for yield loss in VLSI manufacturing. The transformation of contaminating particles into defects and then electrical faults is a very complex process which depends on the defect location, size, material, and the underlying IC topography. An efficient defect macromodeling methodology based on the rigorous two-dimensional (2-D) topography simulator METROPOLE, has been developed to allow the prediction and correlation of the critical physical parameters (material, size, and location) of contamination in the manufacturing process to device defects. The results for a large number of defect samples simulated using the above approach were compared with the data gathered from the AMD-Sunnyvale fabline. A good match was obtained indicating the accuracy for our method of developing contamination to defect propagation/growth macromodels.